1. Field of the Invention
The present invention relates to a liquid crystal display device and a method of fabricating the same, and more particularly, to a line on glass (LOG) type liquid crystal display device and a method of fabricating the same to lower a resistance of a LOG-type pad and to facilitate the carrying out of an associated alignment process.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device displays images by individually supplying data signals to liquid crystal cells arranged in a matrix configuration and controlling light transmittance of the liquid crystal cells. The liquid crystal has a dielectric anisotropy that utilizes an electric field to display a picture. The LCD includes a liquid crystal display panel including the liquid crystal cell matrix arrangement and a driving circuit for driving the liquid crystal display panel.
The driving circuit includes a gate driver for driving gate lines of the liquid crystal display panel, a data driver for driving data lines of the liquid crystal display panel, a timing controller for controlling a driving timing of the gate driver and the data driver, and a power supply for supplying power signals required for driving the liquid crystal display panel and the driving circuit.
The data driver and the gate driver, separated into a plurality of integrated circuits (IC's), are typically manufactured in the shape of a standard chip. Each of these integrated drive IC's is mounted in an open IC area of a tape carrier package (TCP) or in a base film of the TCP by a chip on film (COF) system, and is electrically connected to the liquid crystal display panel by a tape automated bonding (TAB) system. Alternatively, the drive IC may be mounted directly on the liquid crystal display panel by a chip on glass (COG) system. The timing controller and the power supply are also typically manufactured into the shape of a standard chip to be mounted onto a main printed circuit board (PCB).
The drive IC's connected to the liquid crystal display panel by the TCP are connected, via a flexible printed circuit (FPC) and a sub-PCB, to the timing controller and the power supply on the main PCB. More specifically, the data drive IC's receive data control signals and pixel data from the timing controller mounted onto the main PCB and power signals from the power supply via the FPC and the data PCB. The gate drive IC's receive gate control signals from the timing controller mounted onto the main PCB and power signals from the power supply mounted on the main PCB by way of the PCB.
The drive IC's mounted onto the liquid crystal display panel by the COG system receive control signals from the timing controller mounted on the main PCB and power signals from the power supply mounted on the main PCB through the FPC and line on glass (LOG) type signal lines provided at the liquid crystal display panel.
In recent times, even when the drive IC's are connected, via the TCP, to the liquid crystal display panel, LCD arrangements have begun to adopt the LOG-type signal lines to eliminate the inclusion of an unnecessary PCB, thereby reducing the device thickness to result in an overall thinner device. In particular, the gate PCB, which delivers a relatively small number of signals, is removed from the LCD device arrangement. Accordingly, signal lines for applying gate control signals and power signals to the gate drive IC's are provided on the liquid crystal display panel in a LOG type arrangement. As a result, the gate drive IC's mounted in the gate TCP receive the control signals from the timing controller and the power signals from the power supply by way of the main PCB, the FPC, the data PCB, the data TCP, the LOG-type signal lines and the gate TCP in turn.
More specifically, FIG. 1 shows a related art line on glass (LOG) type liquid crystal display arrangement. As shown in FIG. 1, a LOG-type LCD, in which the gate PCB has been removed, includes a main PCB 20 provided with a timing controller 22 and a power supply 24, a data PCB 16 connected, via a FPC 18, to the main PCB 20, a data TCP 12 mounted with a data drive IC 14 and connected between the data PCB 16 and a liquid crystal display panel 6, and a gate TCP 8 mounted with a gate drive IC 10 and connected to the liquid crystal display panel 6.
In the liquid crystal display panel 6, a lower array substrate 2 is joined to an upper array substrate 4. Liquid crystal is injected between the lower and upper array substrates. This liquid crystal display panel 6 is provided with liquid crystal cells driven independently by thin film transistors for each area defined by intersections between gate lines GL and data lines DL. Each of the thin film transistors applies a pixel signal from the data line DL to the liquid crystal cell in response to a scanning signal from the gate line GL.
The data drive IC 14 is connected, via the data TCP 12 and data pads of the liquid crystal display panel, to the data lines DL. The data drive IC 14 converts digital pixel data into analog pixel signals to apply them to the data lines DL. In this regard, the data drive IC 14 receives data control signals, pixel data signals and power signals from the timing controller 22 and the power supply 24 mounted onto the main PCB 20 by way of the data PCB 16 and the FPC 18.
The gate drive IC 10 is connected, via the gate TCP 8 and gate pads of the liquid crystal display panel 6, to the gate lines GL. The gate drive IC 10 sequentially applies a scan signal to the gate lines GL so that the liquid crystal cells arranged in the matrix configuration can be selected line-by-line. The gate drive IC 10 applies a gate high voltage VGH scan signal when sequentially applying the scan signal to select a liquid crystal cell line. Further, the gate drive IC 10 applies a gate low voltage VGL to the remaining gate lines GL when the gate high voltage VGH has been supplied to a selected line.
Accordingly, the gate control signals and the power signals from the timing controller 22 and the power supply 24 on the main PCB 20 are applied, via the FPC 18 and the data PCB 16, to the data TCP 12. The gate control signals and the power signals supplied to the data TCP 12 are then applied, via a LOG-type signal line 26 provided at the edge area of the lower array substrate 2, to the gate TCP 8. The gate control signals and the power signals applied to the gate TCP 8 are supplied, via input terminals of the gate drive IC 10, into the gate drive IC 10. Further, the gate control signals and the power signals are output from the gate drive IC 10 via output terminals of the gate drive IC 10, and applied, via the gate TCP 8 and the LOG-type signal line 26, to a gate drive IC 10 mounted in the subsequent gate TCP 8.
The LOG-type signal line 26 typically includes signal lines for supplying direct current driving voltages from the power supply 24, such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND and a base driving voltage VCC. Also supplied by the LOG-type signal lines are gate control signals from the timing controller 22, such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE.
A first LOG pad 32 extended from one end of the related art LOG-type signal line 26 is connected to a first supply pad of the first data TCP 12 for supplying the gate driving signals, whereas a second LOG pad 38 extended from other end of the LOG-type signal line 26 is connected to a second supply pad of the gate TCP 8.
FIG. 2 is a detailed view of LOG pads for connecting to the TCPs shown in FIG. 1. As shown in FIG. 2, at least one dummy pad 40 is provided between the first and second LOG pads 32 and 38. The dummy pads 40 are provided to improve the adhesive force with respect to at least one of the gate TCP 8 and the data TCP 12.
Each of the first and second LOG pads 32 and 38 of the related art display panel has one input terminal and is formed in the shape of a stripe. In this arrangement, since a contact area between an input terminal of the first LOG pad 32 and an output terminal of the first supply pad and a contact area between an input terminal of the second LOG pad 38 and an output terminal of the second supply pad are small, the resultant contact resistance is relatively high. As a result, the resultant line resistance of the LOG-type signal line 26 connected with the first and second LOG pads 32 and 38 also is relatively high.
Moreover, a problem results in that, because the first and second LOG pads 32 and 38 have a relatively small width, it is not easy to align the first and second LOG pads with the first supply pad of the data TCP and the second supply pad of the gate TCP when the LOG pads are brought into contact with their respective supply pad.